A process for producing printed wiring boards in which an electrically conductive layer is formed only by plating without using a copper foil as the electrically conductive layer has been known as the method of forming a circuit with a narrow wire distance (e.g., Patent Document 1). Hereinafter, this method will be described specifically (hereinafter, such a method will be referred to also as the “method of forming a circuit by plating process”).
First as shown in FIG. 7A, a multilayer circuit board 43 is obtained by lamination molding of prepregs 41 and an internal-layer circuit board 42 having an internal layer circuit 42a formed, and the surface 43a thereof is subjected to a roughening treatment with an oxidizing agent such as potassium permanganate. The roughening treatment is carried out for improvement in the peel strength to an electroless plating layer formed on the surface 43a of the multilayer circuit board 43. Then as shown in FIG. 7B, a hole 44a for forming a through hole 44 is formed in the multilayer circuit board 43. As shown in FIG. 7C, the surface of the hole 44a is made conductive by an electroless plating treatment of the multilayer circuit board 43 having the hole therein, and simultaneously, an electroless plating layer 45 is formed on the surface 43a of the multilayer circuit board 43. Then as shown in FIG. 7D, an electrolytic plating layer 46 is formed on the electroless plating layer 45 by an electrolytic plating treatment. As shown in FIG. 8A, a resist 47 is then formed in the circuit-forming region on the electrolytic plating layer 46. Then as shown in FIG. 8B, regions of the electrolytic plating layer 46 and the electroless plating layer 45 on which the resist 47 is not formed are removed. As shown in FIG. 8C, removal of the resist 47 for example with an alkaline solution gives a multilayer printed wiring board 50 having an external layer circuit 48 formed.
According to such a method, because the thickness of the electrically conductive layer is equivalent only to the thickness of the electroless plating layer 45 and the electrolytic plating layer 46, it is possible to form a thin electrically conductive layer, for example of approximately 20 μm in thickness. In forming a circuit with a narrow wire distance by etching such a thin electrically conductive layer, because the thickness of the electrically conductive layer is small, the etchant easily reaches the insulator substrate surface, resulting in reducing residual of the conductor on the insulator substrate surface and assuring preservation of the interwire insulation sufficiently. However, mass production of the printed wiring board by using such a plating process had a problem of low yield. Specifically when the insulation resistance between non-conductive circuits is measured during a quality inspection for the multilayer printed wiring board obtained, the insulation resistance fluctuated significantly, and it was thus difficult to obtain a printed wiring board having an insulation resistance larger than its standard value.    Patent Document 1: WO2005/104638